1. Field of the Invention
This invention relates to reference timing circuits and, more particularly, to circuits for creating a linear time reference.
2. Description of the Related Art
Electrical circuits often require access to precise timing information for proper operation. In the automatic test equipment (ATE) industry, it is desirable to create a linear time reference that is capable of producing timing edges at predetermined intervals within one period of a reference clock. The timing edges are used by a pattern generator to create a sequence of data codes for drivers used to create a number of different edges (high, low, open) for a device under test (DUT).
One method to accomplish a linear program delay step over one full clock period P is to use an ideal voltage ramp to compare to a digital-to-analog (DAC) output. The comparison would switch from low to high or from high to low when the ramp voltage exceeds a programmed DAC output. A different delay may be chosen by programming the DAC to output a different voltage level for comparison with the ideal voltage ramp. One example implementation of this method is illustrated in U.S. Pat. No. 6,242,959. In this implementation, a ramp comparator circuit and DAC having a programmable delay are used to drive a one-shot circuit in a programmable delay circuit (PDC). Unfortunately, creating the highly linear ramp is difficult. Also, implementations using an ideal voltage ramp may have refire limitations that require a settling period after reset.
A need continues to exist, therefore, for a linear time reference that has fast refire.